1. Field of the Invention
The present invention relates to a shift register circuit and a display drive device comprising the circuit, and particularly to a shift register circuit and a display drive device that are well applied to a drive circuit of a display device such as a liquid crystal display device.
2. Description of the Related Art
In recent years, there has been remarkable prevalence of information equipment such as a computer, a cellular phone, or a personal digital assistant (PDA) and an image processing related equipment such as a digital video camera, a digital still camera, or a scanner. In such equipment, a liquid crystal display (LCD) is frequently used as display means.
For example, an active matrix liquid crystal display device is configured as follows. Display pixels (liquid crystal pixels) equipped with pixel transistors such as thin film transistors are arranged in a matrix shape. Scanning lines are sequentially established in an active state by means of a gate driver with respect to a display panel equipped with scanning lines for connecting display pixels in a row direction and data lines for connecting them in a columnar direction. A predetermined signal voltage is applied to each of the data lines by means of a source driver; and then, a signal voltage according to image information is written into display pixels established in an active state, thereby controlling an alignment state of liquid crystals in the display pixels so as to display desired image information at a predetermined contrast. Here, for example, in the gate driver, a shift register circuit is provided as a constituent element for sequentially outputting scan signals for establishing scanning lines in an active state. In addition, a shift register circuit for setting a timing of sampling and acquiring display data to be supplied, in association with data lines is provided in the source driver.
FIG. 8A is a circuit diagram showing an exemplary construction of a conventional shift register circuit.
FIG. 8B is a timing chart for explaining an operation of the shift register of FIG. 8A.
FIG. 9A is a circuit diagram showing a construction of a signal holding section that configures the conventional shift register.
FIG. 9B is a timing chart for explaining an operation of the signal holding section of FIG. 8A.
The shift register circuit, as shown in FIG. 8A, is constructed such that a plurality (plural stages) of signal holding sections are cascade-connected in series. Then, the signals held in the signal holding sections are externally outputted as an output signal OUTn and are sequentially transferred (shifted) to signal holding sections of a subsequent stage.
Each of the signal holding sections, as shown in FIG. 8A, is configured by a combination of a set/reset type flip flop FFn and a push/pull circuit composed of two MOS transistors T1n and T2n (n=1, 2, 3, 4, . . . ).
That is, connection is established such that an input signal IN is supplied to a set signal input terminal S of the flip flop FFn and a reset signal RST is supplied to a reset signal input terminal R. In addition, the first and second MOS transistors T1n and T2n that configure the push/pull circuit are connected in series between a terminal applied with a predetermined clock signal CK and a power supply terminal applied with a low electric potential power supply Vss. A gate electrode of the first MOS transistor T1n is connected to an output terminal Q of the flip flop FFn, and a gate electrode of the second MOS transistor T2n is connected to an inverted output terminal Q of the flip flop FFn. Then, an output signal OUT is outputted from a connection contact between both of the MOS transistors T1n and T2n. 
In the thus constructed signal holding section, as shown in the timing chart of FIG. 8B, when the input signal IN supplied to the set signal input terminal S of the flip flop FFn is obtained at a high level, the flip flop FFn is set; a high level signal is outputted from the output terminal Q thereof and a low level signal is outputted from the inverted output terminal Q. The state of the output signal of this flip flop FFn is maintained even if the input signal reverts to a low level.
Then, when a reset signal RST supplied to the reset signal input terminal R is obtained at a high level, the signal is reset, a low level signal is outputted from the output terminal Q of the flip flop FFn, and then, a high level signal is outputted from the inverted output terminal Q.
When a high level signal is thus outputted from the output terminal Q of the flip flop FFn in accordance with the high level of the input signal IN, a high level voltage is applied to a gate electrode of the first MOS transistor T1n of the push/pull circuit, and then, the first MOS transistor T1n is turned ON. In addition, at this time, a low level signal is outputted from the inverted output terminal Q of the flip flop FFn. Thus, a low level voltage is applied to the gate electrode of the second MOS transistor T2n of the push/pull circuit, and then, the second MOS transistor T2n is turned OFF. At this time, when a high level pulse signal CK is supplied to the push/pull circuit, an output signal OUT is obtained at a high level.
Then, when the reset signal RST is obtained at a high level, a low level signal and a high level signal are outputted from the output terminal Q and the inverted output terminal Q, respectively, of the flip flop FFn. In this manner, the first MOS transistor T1n is turned OFF, and then, the second MOS transistor T2n is turned ON. Therefore, the output signal OUT is obtained at a low level.
The shift register circuit, as shown in FIG. 8A, is constructed by cascade-connecting a plurality of the signal holding sections having the above construction in series. That is, an output signal OUTn is acquired from a push/pull circuit of a signal holding section of the n-th stage and the resulting signal is supplied to a set terminal S of a flip flop FFn+1 of a signal holding section of the n+1-th stage. Connection to the reset terminal R of the flip flop FFn of the signal holding section of the n-th stage is established so as to feed back an output signal OUTn+1 from the signal holding section of the n+1-th stage. Here, a predetermined start signal ST is supplied to the set terminal S of the flip flop FFn of a signal holding section of a first stage. In addition, a reset signal is externally supplied to the reset terminal R of a flip flop FFn of a signal holding section of a final stage. Then, a first pulse signal CK1 is supplied to a push/pull circuit of a signal holding section of an odd-numbered stage and a second pulse signal CK2 having an inverted waveform of the first pulse signal CK1 is supplied to a push/pull circuit of a signal holding section of an even-numbered stage.
According to the thus constructed shift register circuit, as shown in the timing chart of FIG. 8B, after the start signal ST has been supplied, high level output signals OUT1, OUT2, OUT3, OUT4, . . . are sequentially transferred (shifted), and then outputted in synchronism with a high level applying timing of the pulse signals CK1 and CK2. Therefore, for example, when scan signals based on these output signals OUT1, OUT2, OUT3, OUT4, . . . are sequentially applied to scan lines of the liquid crystal display device, a line sequential selection operation can be made such that the display pixels connected to the scan lines are established in an active state on a row by row basis.
The first MOS transistor T1n of the push/pull circuit in this signal holding section plays an important role in signal output and transfer to a next stage. That is, it is no exaggeration to say that the characteristics of this first MOS transistor T1n determine the performance of the whole shift register circuit.
On the other hand, it has been researched and developed that drive circuits such as a gate driver and a source driver in an active matrix liquid crystal display device are integrally formed on a display panel substrate (TFT substrate) by means of thin film transistors made of amorphous silicon (a-Si) or poly-silicon (p-Si), thereby promoting reduction in cost and thickness of the display device. In particular, amorphous silicon is advantageous in cost reduction because it can be formed at the same time when TFT configuring pixels is formed.
However, in the case where the signal holding section as described above is composed of MOS transistors made of amorphous silicon TFTs or poly-silicon TFTs, it is experimentally known that, in such MOS transistors, threshold value characteristics vary due to eccentricity of positive and negative polarities of a time integral value (or integrated voltage) of a signal level applied to a gate electrode, whereby a change with time at which an ON current is lowered is comparatively great with respect to transistors made of single-crystal silicon. Therefore, in the case where the shift register circuit is constructed using such MOS transistors, in particular, the characteristics of the first MOS transistor T1n of the push/pull circuit that plays an important role in signal output and transfer to a next stage deteriorates with time; the signal level of the output signal OUT is lowered with time; a switching operation of each transistor is not properly made; and a malfunction of the shift register circuit or deterioration of operational characteristics may occur.